An output condition monitor apparatus of this kind is disclosed in Japanese Patent Laid-Open Patent No. 178840/1983. FIG. 14 of the present application is a circuit diagram of the fundamental configuration of a velocity sustaining apparatus making use of this conventional output condition monitor apparatus. The illustrated apparatus comprises an electronic control unit, or central processing unit (CPU), that consists of a microcomputer fabricated on a single integrated circuit chip. The CPU receives output signals from various switches including a reed switch for detecting the velocity of the vehicle, a clutch switch for producing a signal when the driver presses down on the clutch pedal, a brake switch for producing a signal when the driver presses down on the brake pedal, a set switch, and a resume switch. Also, the output signal from a vacuum switch disposed in the surge tank is applied to the CPU. A solenoid that is used with a control valve for controlling a vacuum actuator, a solenoid for use with a vent valve, and a solenoid for use with a release valve are connected with the output of the CPU via their respective driver circuits. These three solenoids are connected with the inputs of their respective detector circuits, which are coupled to the CPU.
FIG. 14 shows a portion of the configuration as described above. Each solenoid VL is energized by a driver circuit comprising a pull-up resistor R1 and a switching transistor Q1, the solenoid VL being used with a valve that is controlled by the CPU. A detector circuit for detecting the signal delivered from the solenoid VL to the CPU comprises a pull-up resistor R2 and a switching transistor Q2. A diode FD is used to produce a flywheel effect.
In the structure constructed as described above, when the output from the CPU goes high, the transistor Q1 is turned on. Then, the solenoid VL is energized to actuate the valve. At this time, the transistor Q2 is not conducting, and the input to the CPU is at high level. When the output from the CPU goes low, the transistor Q1 is turned off to deenergize the solenoid VL for use with the valve. At this time, the transistor Q2 conducts, and the input to the CPU goes low. Under this normal condition, the input to the CPU coincides with the output from the CPU.
If the solenoid VL that acts on the valve breaks, the transistor Q2 always fails to conduct. Under this condition, the input to the CPU is at high level and retained at this level even if the output from the CPU goes low. Thus, the disagreement between the input and the output is detected by a comparator means. If this state persists over a given period, then the condition is regarded as abnormal, followed by inhibition of the operation of the CPU. The same principles apply when the solenoid VL for use with the valve is short-circuited.
However, a problem takes place when the solenoid VL is short-circuited. Specifically, whenever the solenoid VL is short-circuited, the transistor Q2 conducts, bringing the signal applied to the CPU to low state which is not altered even if the output from the CPU goes high. The disagreement between them is detected by the comparator means. If this condition persists over a given period, it is judged to be abnormal. Then, the control operation will be stopped, but the recurring output from the CPU permits such a control operation for a short time. Especially, when such a short-circuit takes place, an abnormal large current flows repeatedly through the short-circuited location.